An Online Unsupervised Structural Plasticity Algorithm for Spiking Neural Networks

In this article, we propose a novel Winner-Take-All (WTA) architecture employing neurons with nonlinear dendrites and an online unsupervised structural plasticity rule for training it. Further, to aid hardware implementations, our network employs only binary synapses. The proposed learning rule is inspired by spike time dependent plasticity (STDP) but differs for each dendrite based on its activation level. It trains the WTA network through formation and elimination of connections between inputs and synapses. To demonstrate the performance of the proposed network and learning rule, we employ it to solve two, four and six class classification of random Poisson spike time inputs. The results indicate that by proper tuning of the inhibitory time constant of the WTA, a trade-off between specificity and sensitivity of the network can be achieved. We use the inhibitory time constant to set the number of subpatterns per pattern we want to detect. We show that while the percentage of successful trials are 92%, 88% and 82% for two, four and six class classification when no pattern subdivisions are made, it increases to 100% when each pattern is subdivided into 5 or 10 subpatterns. However, the former scenario of no pattern subdivision is more jitter resilient than the later ones.Comment: 11 pages, 10 figures, journa

Liquid State Machine with Dendritically Enhanced Readout for Low-power, Neuromorphic VLSI Implementations

In this paper, we describe a new neuro-inspired, hardware-friendly readout stage for the liquid state machine (LSM), a popular model for reservoir computing. Compared to the parallel perceptron architecture trained by the p-delta algorithm, which is the state of the art in terms of performance of readout stages, our readout architecture and learning algorithm can attain better performance with significantly less synaptic resources making it attractive for VLSI implementation. Inspired by the nonlinear properties of dendrites in biological neurons, our readout stage incorporates neurons having multiple dendrites with a lumped nonlinearity. The number of synaptic connections on each branch is significantly lower than the total number of connections from the liquid neurons and the learning algorithm tries to find the best 'combination' of input connections on each branch to reduce the error. Hence, the learning involves network rewiring (NRW) of the readout network similar to structural plasticity observed in its biological counterparts. We show that compared to a single perceptron using analog weights, this architecture for the readout can attain, even by using the same number of binary valued synapses, up to 3.3 times less error for a two-class spike train classification problem and 2.4 times less error for an input rate approximation task. Even with 60 times larger synapses, a group of 60 parallel perceptrons cannot attain the performance of the proposed dendritically enhanced readout. An additional advantage of this method for hardware implementations is that the 'choice' of connectivity can be easily implemented exploiting address event representation (AER) protocols commonly used in current neuromorphic systems where the connection matrix is stored in memory. Also, due to the use of binary synapses, our proposed method is more robust against statistical variations.Comment: 14 pages, 19 figures, Journa

Analysis of Various DCVSL Structures and Implementation of Full Adder with Them

The Differential Cascode Voltage Switch Logic (DCVSL) is a CMOS circuit technique which has potential advantages over conventional NAND/NOR logic in terms of power dissipation, circuit delay, layout density and logic flexibility. In this paper, a detailed comparison of all the DCVSL structures are provided including the implementation of Full Adder circuit with the help of those DCVSL structures, which includes Static DCVSL, Dynamic DCVSL and Modified DCVSL. The performance analysis is done in Cadence Virtuoso 90nm CMOS Technology. The working of these DCVSL structures is based on the concept of ‘Multiplexer’. A multiplexer also known as ‘mux’, which is a device where from a number of input signals, selection is done. It is basically a combinational logic circuit. The multiplexer is a unidirectional device, which is used in applications where a data must be switched from multiple sources to a destination. The analysis of all these DCVSL structures is followed by the implementation of Full Adder. Adders are the building blocks in computer systems. Digital Computer Systems widely uses Arithmetic operations. Addition is a necessary arithmetic operation, which is also the root for arithmetic operation such as multiplication. Similarly, adding another XOR gate, the basic adder cell can be modified to function as subtractor, which can be used for division. Therefore, 1-bit Full Adder cell is the ultimate and simple block of an arithmetic unit of a system. So, the basic 1-bit Full Adder cell must be improved, so that the performance of the digital circuits. In VLSI, there is always a trade-off between speed and power dissipation. One parameter is improved, the other gets degraded. Hence, the parameter power delay product is introduced. So, to achieve speeds, high drivability hybrid-DCVSL design methodologies are used to build adder cell in this work. The DCVSL gates produces both complementary and true outputs using single gate architecture. And, the multipliers in the design are based on the pass transistor logic (PTL), because these occupies less chip area per component and also are simple to construct. The parameters compared are power dissipation, propagation delay time, power delay product, transistor number and power dissipation (average). The Static DCVSL structure produces best result in terms of power dissipation, delay and power delay product. Whereas, in case of the Adder circuit, the power consumption is best for the Dynamic DCVSL Adder, along with the delay and the power delay product for the output Sum; but for the output Cout, the best option is Static DCVSL Adder, as the delay and the power delay product is least in this case

N-Acetylglucosamine-inducible CaGAP1 encodes a general amino acid permease which co-ordinates external nitrogen source response and morphogenesis in Candida albicans

Candida albicans is able to grow in a variety of reversible morphological forms (yeast, pseudohyphal and hyphal) in response to various environmental signals, noteworthy among them being N-acetylglucosamine (GlcNAc). The gene CaGAP1, homologous to GAP1, which encodes the general amino acid permease from Saccharomyces cerevisiae, was isolated on the basis of its induction by GlcNAc through differential screening of a C. albicans genomic library. The gene could functionally complement an S. cerevisiae gap1 mutant by rendering it susceptible to the toxic amino acid analogue mimosine in minimal proline media. As in S. cerevisiae, mutation of the CaGAP1 gene had an effect on citrulline uptake in C. albicans. Northern analysis showed that GlcNAc-induced expression of CaGAP1 was further enhanced in synthetic minimal media supplemented with single amino acids (glutamate, proline and glutamine) or urea (without amino acids) but repressed in minimal ammonium media. Induction of CaGAP1 expression by GlcNAc was nullified in C. albicans deleted for the transcription factor CPH1 and the hyphal regulator RAS1, indicating the involvement of Cph1p-dependent Ras1p signalling in CaGAP1 expression. A homozygous mutant of this gene showed defective hyphal formation in solid hyphal-inducing media and exhibited less hyphal clumps when induced by GlcNAc. Alteration of morphology and short filamentation under nitrogen-starvation conditions in the heterozygous mutant suggested that CaGAP1 affects morphogenesis in a dose-dependent manner